@camelcdr
> Consider scalar1, m8rvv, scalar2. In a 4-wide design, the "latency" focuses RVV implementation would decode scalar2 after 3 cycles, but the "throughput" one on the first.
That's assuming the latency-focused design doesn't predict the vector config, which is where the rabbit hole of edge cases comes from...
> Consider scalar1, m8rvv, scalar2. In a 4-wide design, the "latency" focuses RVV implementation would decode scalar2 after 3 cycles, but the "throughput" one on the first.
That's assuming the latency-focused design doesn't predict the vector config, which is where the rabbit hole of edge cases comes from...